1. Field of the Invention
The present invention relates to a circuit for buffering and synchronizing the memory column address strobe (CAS) signals and interlocking the data latch with the CAS signals of a computer system.
2. Description of the Related Art
Modern computer systems are becoming more modularized wherein the different components or subsystems of the computer system are provided on separate and removable circuit boards, or modules, which are all coupled together through a main system or mother board. The mother board contains a plurality of connectors to provide an interconnection network between the components or subsystems that comprise the entire computer system. The vital subsystems which are traditionally located on the motherboard, such as main memory or the central processing unit (CPU) and supporting logic, are now being placed on the removable modules.
There are many reasons for and benefits of modularization of computer systems. The entire computer system is not taken out of service for a significant period of time due to the failure of any given subsystem since the faulty subsystem can be readily replaced without having to service the entire computer system. The module that contains the faulty subsystem is removed and replaced such that the computer system can be immediately placed back into service. Another benefit is that since many computer systems are designed for particular purposes or specific applications, a modularized computer system may be tailored or programmed to meet the needs of the specific application.
For example, some computer systems need more processing capability, such that more of the modules or subsystems comprise processors, while other computer systems need more memory or extended input/output (I/O) capability. Modularization allows an easier way to upgrade a given computer system. For example, a different processor subsystem can replace or supplement the existing processor subsystem, or a new memory board can supplement or replace the existing memory board to provide enhanced memory capability.
One problem that arises in complex computer systems, particularly modularized computers, is timing variances due to complicated signal traces and a plurality of connectors between a source and a receiver. As a result of the added complexity of modularization, for example, some signals are delayed longer relative to other signals, causing skew problems wherein signals arrive at different locations at different times. Timing requirements between two signals may be violated if one signal is skewed relative to another, resulting in invalid data and improper operation of a computer system.
Skew problems are especially difficult to prevent between the host and memory data buses. A memory controller, which is usually provided to facilitate transfer of data between buses, typically provides row and column address signals to memory comprising dynamic random access memory (DRAMs), as well as latch enable signals to latchable transceiver data bus buffers (BB) placed between the host data bus and the memory data bus. The data buffers provide isolation between the host and memory data buses and allow control of the direction of flow of information between the data buses. The row and column address signals, or strobes, should be synchronized with the latch enable signals to meet the timing requirements of the data buffers and the (DRAMs). In a modularized system, skew problems can arise between the latch enable signal provided to the data buffers and the column address strobe (CAS) signals provided to the DRAMs. If the latch enable signals are negated prematurely before set-up timing requirements to the bus buffers are met, it is very likely that invalid data will be latched into the data buffers, causing improper operation.
One possible solution to the skew problems which arise in computer systems is to slow the entire system down by adding a clock cycle or a wait state such that the critical signals remain valid for an extra clock state. This solution, however, is undesirable since there is a decrease in performance of the overall computer system. It is desirable, therefore, to provide a solution to the timing skew problems which arise in a complex computer system without slowing it down.
Memory is typically organized into a plurality of DRAMs wherein each bit of data and each DRAM is accessible through a column and a row address signal. In many computer systems, it is desirable that the memory controller provide a separate CAS signal for each byte of data on the data bus so that each byte of data is individually accessible. Typically, all the individual CAS signals from the memory controller are the same for a read operation. Each CAS signal involves a plurality of DRAM semiconductor chips so that the CAS signals must be duplicated and buffered to provide enough drive for each DRAM. The duplicated CAS signals provided to the DRAMs represent the same CAS signals and it is desirable that they be asserted and negated at substantially the same time to assure proper data latching. It is desirable that the duplicated CAS signals provided to the DRAMs are asserted as soon as possible with as little time delay from when the memory controller asserts the original CAS signal, and negated at approximately the same time as the memory latch enable signal provided to the data buffer is negated. Further, the latch enable must not be negated until the data has had time to become valid and meet the setup time of the bus buffer, which with 80 nsec DRAMs and the preferred bus buffer is approximately 28.5 nsec, worst case, from the falling edge of the CAS signal.